The semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density, higher performance, and lower cost. In the course of integrated circuit (IC) evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Despite advances in materials and fabrication, scaling planar devices such as the conventional MOSFET has proven challenging. For example, such scaling-down is subject to produce a relatively limited area (i.e., small area) that can be used to connect a transistor to other components. As such, the limited area may disadvantageously impact the junction resistance, which in turn may degrade a transistor's switching speed.